Elimination of accumulation charge effects for high-resistive silicon substrates

Author

Jansman, A.B.M. ; van Beek, J.T.M. ; van Delden, M.H.W.M. ; Kemmeren, A.L.A.M. ; Dekker, A. Den ; Widdershoven, F.P.

Author_Institution

Philips Res. Labs., Eindhoven, Netherlands

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

3

Lastpage

6

Abstract

A dedicated silicon process, called PASSI/spl trade/, was developed for passive functions in the GHz regime. The process, using high-resistive silicon with a SiO/sub 2/ top layer as a carrier, is fully compatible with common silicon infrastructures. While the passives perform far better than passives integrated in CMOS or BICMOS chips, their performance is limited by accumulation of charge underneath the SiO/sub 2/ layer. A very effective way to diminish the influence of. this charge is an implantation that creates traps at the Si/SiO/sub 2/ interface, thus reducing the charge mobility. The capacitors and inductors on wafers that were subject to such an implantation step can no longer be distinguished from their counterparts on insulating substrates.

Keywords

MIM devices; carrier mobility; elemental semiconductors; interface states; ion implantation; silicon; silicon compounds; thin film capacitors; thin film inductors; MIM-capacitor; PASSI thin film process; Si-SiO/sub 2/; accumulation charge effect elimination; charge accumulation; charge mobility reduction; heavy ion implantation; high-resistive silicon substrates; interface traps; passive functions; single-winding inductors; Artificial intelligence; BiCMOS integrated circuits; Conductivity; Dielectric substrates; Fabrication; Frequency; Inductors; Insulation; MOS capacitors; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256799

Filename

1256799