MC simulation of strained Si/SiGe devices

Author

Jungemann, C. ; Meinerzhagen, B.

Author_Institution

Bremen Univ., Germany

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

9

Lastpage

14

Abstract

Transport in strained Si N- and PMOSFETs with gate lengths from 250 to 50 nm is investigated by full-band MC (Monte Carlo) device simulation. Performance improvement by strain is found for both device types, and even for the shortest gate length the on-current is enhanced by about 30% compared to the unstrained case. Thus, these simulations predict that the performance advantage of strained Si MOSFETs will scale well into the deca-nanometer gate length range. This seems to be due to the reduction in scattering by strain, leading to quasi-ballistic transport and enhanced charge carrier velocities at the source side injection point of the inversion channel.

Keywords

Ge-Si alloys; MOSFET; Monte Carlo methods; carrier mobility; elemental semiconductors; semiconductor device models; semiconductor materials; silicon; 250 to 50 nm; MC simulation; Monte Carlo model; Si-SiGe; charge carrier velocity enhancement; gate length; inversion channel source side injection point; on-current enhancement; quasi-ballistic transport; strain induced scattering reduction; strained NMOSFET; strained PMOSFET; strained Si/SiGe devices; Calibration; Capacitive sensors; Doping; Germanium silicon alloys; MOSFETs; Microscopy; Scattering; Semiconductor process modeling; Silicon germanium; Strain measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256800

Filename

1256800