A novel ultra-low power reset/read-out technique for megapixels current-mode CMOS imagers

A novel reset/read-out technique is presented for current-mode ultra-low power megapixel CMOS imagers. In the proposed technique, the reset and readout phases occur simultaneously: as a single pixel is being read-out another pixel is being reset. Such a strategy is shown to result in a significant reduction in power consumption. Furthermore, power consumption becomes independent of both read-out speed and imager array size, while still allowing for on read-out FPN correction along with external electronic shutter control. Its potential integration into CMOS imagers, is demonstrated through the full custom design of a programmable 32/spl times/32 current-mode CMOS imager in AMIS CMOS 0.35 /spl mu/m technology.