Title :
A substrate triggered lateral bipolar circuit for high voltage tolerant ESD protection applications
Author :
Smith, Jeremy C.
Author_Institution :
Technol. Data Syst. Lab., Motorola Inc., Austin, TX, USA
Abstract :
In this work, a substrate triggered HV tolerant lateral NPN (LNPN) design is presented for a fully salicided, 0.35 /spl mu/m, 90 /spl Aring/ gate oxide, thin-epi, retrograde n-well, bulk CMOS technology. The design is highly independent of power rail capacitance, exhibits reduced pin leakages at elevated temperatures and is fully compatible with the baseline process. The design has been shown to achieve over 2 kV of HBM performance for all positive discharge stress modes, which are the most difficult to protect against in epi processes.
Keywords :
CMOS integrated circuits; bipolar integrated circuits; electrostatic discharge; integrated circuit design; integrated circuit reliability; leakage currents; protection; 0.35 micron; 2 kV; 90 angstrom; HBM performance; SiO/sub 2/-Si; baseline process compatibility; epi processes; high voltage tolerant ESD protection; pin leakage; positive discharge stress modes; power rail capacitance; salicided retrograde n-well bulk CMOS technology; substrate triggered HV tolerant lateral NPN design; substrate triggered lateral bipolar circuit; CMOS technology; Capacitance; Circuits; Electrostatic discharge; Power supplies; Process design; Protection; Rails; Substrates; Voltage;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998
Conference_Location :
Reno, NV, USA
Print_ISBN :
1-878303-91-0
DOI :
10.1109/EOSESD.1998.737023
