Title :
Wafer-level packaging technology for extended global wiring and inductors
Author :
Carchon, G. ; Carbonell, L. ; Jenei, S. ; Van Hove, M. ; Decoutere, S. ; De Raedt, W. ; Maex, K. ; Beyne, E.
Author_Institution :
IMEC, Heverlee, Belgium
Abstract :
Wafer level packaging (WLP) technology, originally introduced for thin film redistribution layers, offers novel opportunities for extended global wiring and passives and has been used to integrate transmission lines and state-of-the-art high Q on-chip inductors on top of a five-levels-of-metal (5 ML) Cu/oxide back-end of line (BEOL) 20/spl Omega/cm silicon process. The transmission lines and inductors are realized above the passivation using thick post-processed dielectric (BCB, /spl epsiv//sub r/=2.65) and Cu layers. Measurements on the BEOL before and after post-processing show no significant shifts for all 5 metal layers. Post-processed 50/spl Omega/ transmission lines. have losses below -0.1dB/mm@25GHz; a InH inductor has a peak Q-factor of 38 at 4.7GHz with resonance frequency (F/sub res/) of 29GHz, the Q-factor tops 30 over 2.6-8.6GHz. Patterned polysilicon ground shields further improve the performance: a Q-factor increase of 90% was demonstrated at 7GHz for a 2.25nH inductor.
Keywords :
Q-factor; chip scale packaging; inductors; integrated circuit interconnections; back-end of line process; extended global wiring; high speed interconnect lines; on-chip inductors; patterned polysilicon ground shields; peak Q-factor; transmission lines; wafer-level packaging technology; Dielectric measurements; Passivation; Propagation losses; Q factor; Semiconductor thin films; Silicon; Thin film inductors; Transmission line measurements; Wafer scale integration; Wiring;
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
DOI :
10.1109/ESSDERC.2003.1256821
