DocumentCode
2441276
Title
Influence of scribe lane structures on wafer potentials and charging damage
Author
Lukaszek, Wes
Author_Institution
Wafer Charging Monitors Inc., Woodside, CA, USA
fYear
2000
fDate
2000
Firstpage
26
Lastpage
28
Abstract
Results are presented which show that scribe lane structures can exert a significant influence on surface-substrate potentials and J-V characteristics measured on a wafer surface in plasma and ion-implant processes. The implications of this phenomenon for comparison of charging damage results obtained with charging test vehicles and product wafers are also discussed
Keywords
ion implantation; plasma materials processing; surface charging; surface potential; IC manufacturing; charging damage; current-voltage characteristics; ion implantation; plasma processing; scribe lane structure; semiconductor wafer; surface substrate potential; Electrons; Manufacturing processes; Plasma applications; Plasma density; Plasma devices; Plasma materials processing; Plasma measurements; Plasma properties; Process control; Surface charging;
fLanguage
English
Publisher
ieee
Conference_Titel
Plasma Process-Induced Damage, 2000 5th International Symposium on
Conference_Location
Santa Clara, CA
Print_ISBN
0-9651577-4-1
Type
conf
DOI
10.1109/PPID.2000.870578
Filename
870578
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