Device and circuit considerations for high performance SOI technologies

Summary form only given. The insatiable need for higher performance microprocessors has driven the development of high-speed deep-submicron Silicon On Insulator (SOI) CMOS technology. SOI 1.8 V microprocessors are currently produced in IBM´s manufacturing line at 220 nm groundrules, and microprocessors are being developed for 1.5 V-180 nm and 1.2 V-130 nm SOI technologies. These technologies are based on partially-depleted (PD) SOI CMOS transistor designs because fully-depleted SOI transistor designs require excessively thin SOI films for short-channel threshold voltage control and also need alternate workfunction gate materials to achieve required transistor thresholds. Inherent to PD-SOI CMOS transistors is a floating body that needs to be accounted for in transistor design, manufacturing, and circuit design