Title :
Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks
Author :
Voldman, S. ; Geissler, S. ; Nakos, J. ; Pekarik, Jack ; Gauthier, R.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
The impact of MOSFET source/drain junction scaling on the ESD robustness of shallow trench isolation (STI)-defined diode structures is shown for the first time. ESD robustness improvements to STI-bound p/sup +/ diodes using germanium preamorphization and deep B11 implants, and polysilicon-bordered ESD networks are also discussed.
Keywords :
CMOS integrated circuits; MOSFET; amorphisation; electrostatic discharge; elemental semiconductors; integrated circuit design; integrated circuit reliability; ion implantation; isolation technology; optimisation; protection; semiconductor diodes; silicon; CMOS technology; ESD networks; ESD robustness; MOSFET source/drain junction scaling; STI-bound p/sup +/ diodes; STI-defined diode structures; Si; Si:B; Si:Ge; deep B11 implants; germanium preamorphization; polysilicon-bordered ESD networks; polysilicon-bound source/drain diodes; semiconductor process optimization; shallow trench isolation-defined diodes; structural optimization; CMOS technology; Cobalt; Electrostatic discharge; Germanium; Implants; Isolation technology; MOSFET circuits; Robustness; Semiconductor diodes; Very large scale integration;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998
Conference_Location :
Reno, NV, USA
Print_ISBN :
1-878303-91-0
DOI :
10.1109/EOSESD.1998.737034
