DocumentCode :
2441313
Title :
Analysis of laterally asymmetric channel design in fully depleted double gate (DG) SOI MOSFETs for high performance analog applications
Author :
Kranti, A. ; Chung, T.M. ; Flandre, D. ; Raskin, J.P.
Author_Institution :
Microwave Labs., Univ. Catholique de Louvain, Belgium
fYear :
2003
fDate :
16-18 Sept. 2003
Firstpage :
131
Lastpage :
134
Abstract :
Based on analytical modeling, 2D simulation and experimental results, this work demonstrates the potential benefits of using laterally asymmetric channel design over uniform doping in DG SOI MOSFETs for achieving excellent analog performance. We show that the asymmetric channel design in DG MOSFETs makes it possible to achieve a DC gain of 80 dB, an Early voltage of over 1200 V and nearly ideal values (/spl sim/38 V/sup -1/) of transconductance-to-current ratio for L/sub eff/ = 1.64 /spl mu/m, well in excess of those reported so far. Analysis shows new opportunities for realising future high performance analog circuits with GC DG MOSFETs.
Keywords :
MOSFET; semiconductor device models; silicon-on-insulator; 1.64 micron; 1200 V; 80 dB; DG SOI MOSFET; Early voltage; analog MOSFET; fully depleted double gate MOSFET; laterally asymmetric channels; transconductance-to-current ratio; Analog circuits; Analytical models; Degradation; Doping; Gain; Laboratories; MOSFETs; Performance analysis; Semiconductor process modeling; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
Type :
conf
DOI :
10.1109/ESSDERC.2003.1256828
Filename :
1256828
Link To Document :
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