Improvement of data retention time using DRAM cell with metallic shield embedded (MSE)-STI for 90nm technology node and beyond

As the technology node of DRAM goes below 100 nm, the dimensional scaling of the devices greatly influences the major parameters that determine the performance of DRAM. Especially, the reduction of the isolation space in a cell array can deteriorate the characteristics of the cell transistor and storage node junction, which results in a degradation of data retention time. In order to overcome these issues, metallic shield embedded (MSE)-STI has been proposed but has not been realized yet. In this paper, for the first time, we successfully demonstrate a DRAM cell transistor with MSE-STI for the 90 nm DRAM technology node and beyond. As a result, we can obtain a reliable cell transistor with low-doped channel profile, uniform threshold voltage distribution and low junction leakage current, and most importantly,we can greatly improve data retention characteristics.