DocumentCode
2441434
Title
ESD and latch-up characteristics of semiconductor device with thin epitaxial substrate
Author
Suzuki, Teruo ; Sekino, Satoshi ; Ito, Seigo ; Monma, Hideo
Author_Institution
Dept. of Syst. LSI Design, Fujitsu VLSI Ltd., Mie, Japan
fYear
1998
fDate
6-8 Oct. 1998
Firstpage
199
Lastpage
207
Abstract
We have evaluated latch-up and ESD characteristics using substrates which have a relatively thin epi layer of 1 /spl mu/m to 5 /spl mu/m. From the measurement results, we found that latch-up immunity does not necessarily increase as the epi layer becomes thinner. The ESD immunities of both the machine model (MM) and the human body model (HBM) have the same tendency that depends on the epi layer thickness and are weakest when the epi layer thickness is 2 /spl mu/m. By examining the latch-up and ESD immunity measurement results, we found that low resistivity substrates greatly affected these results.
Keywords
CMOS integrated circuits; electrical resistivity; electrostatic discharge; integrated circuit measurement; integrated circuit reliability; semiconductor epitaxial layers; 1 to 5 micron; 2 micron; CMOS devices; ESD; ESD characteristics; ESD immunity; ESD immunity measurement; Si; epilayer thickness; human body model; latch-up characteristics; latch-up immunity; latch-up immunity measurement; machine model; semiconductor device; substrate resistivity; thin epi layer; thin epitaxial substrate; Circuit noise; Circuit testing; Conductivity; Electrostatic discharge; Immune system; Inverters; Large scale integration; Semiconductor devices; Silicon; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998
Conference_Location
Reno, NV, USA
Print_ISBN
1-878303-91-0
Type
conf
DOI
10.1109/EOSESD.1998.737039
Filename
737039
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