Simulation of complete CMOS I/O circuit response to CDM stress

Author

Beebe, Stephen G.

Author_Institution

Adv. Micro Devices, Sunnyvale, CA, USA

fYear

1998

fDate

6-8 Oct. 1998

Firstpage

259

Lastpage

270

Abstract

Enhanced compact modeling is implemented in a commercial simulator to study CMOS circuit response to charged device model (CDM) stress. Procedures for characterization of transistor snapback, oxide breakdown, and package and tester parasitics are detailed. Application to 0.25 /spl mu/m technology SRAM I/O circuits demonstrates effectiveness in analyzing CDM response and quantitatively predicting withstand levels.

Keywords

CMOS memory circuits; SRAM chips; circuit simulation; electric breakdown; electrostatic discharge; integrated circuit modelling; integrated circuit reliability; static electrification; 0.25 micron; CDM response; CDM stress; CMOS I/O circuit CDM stress response simulation; CMOS circuit response; SRAM I/O circuits; SiO/sub 2/-Si; charged device model stress; compact modeling; oxide breakdown; package parasitics; simulator; tester parasitics; transistor snapback; withstand level prediction; Circuit simulation; Circuit testing; Electrostatic discharge; Integrated circuit packaging; Pins; Predictive models; RLC circuits; Random access memory; Semiconductor device modeling; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998

Conference_Location

Reno, NV, USA

Print_ISBN

1-878303-91-0

Type

conf

DOI

10.1109/EOSESD.1998.737046

Filename

737046