Title :
Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield
Author :
Croon, J.A. ; Leunissen, L.H.A. ; Jurczak, M. ; Benndorf, M. ; Rooyackers, R. ; Ronse, K. ; Decoutere, S. ; Sansen, W. ; Maes, H.E.
Author_Institution :
IMEC vzw, Leuven, Belgium
Abstract :
This work experimentally investigates the impact of line-edge roughness (LER) on the intrinsic transistor performance of the MOS transistor. Examined gate lengths range down to 50 nm. To emphasize the impact of LER, transistors with extra rough poly gates are created by e-beam lithography. Assumptions of models, that describe the effects of LER, are tested on transistors with sinusoidal gate-shapes. For the first time, the impact of LER on transistor yield is reported.
Keywords :
MOSFET; electron beam lithography; semiconductor device measurement; semiconductor device models; 50 nm; LER; MOS transistor; MOSFET performance; MOSFET yield; e-beam lithography; gate length; line-edge roughness; sinusoidal gate-shapes; sinusoidally shaped transistors; Cause effect analysis; Degradation; Fluctuations; Lithography; MOSFET circuits; Power measurement; Shape; Smoothing methods; Spectral analysis; Testing;
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
DOI :
10.1109/ESSDERC.2003.1256855
