Author :
Kubicek, S. ; Chen, J. ; Ragnarsson, L-Å ; Carter, R.J. ; Kaushik, V. ; Lujan, G.S. ; Cartier, E. ; Henson, W.K. ; Kerber, A. ; Pantisano, L. ; Beckx, S. ; Jaenen, P. ; Boullart, W. ; Caymax, M. ; DeGendt, S. ; Heyns, M. ; De Meyer, K.
Abstract :
NMOS and PMOS transistors with poly-Si gate electrode and HfO/sub 2/ gate dielectric were fabricated using a conventional self-aligned process flow. Functional transistors with final EOT/spl sim/1.8 nm were obtained down to 70 nm gate lengths using a low thermal budget process without a poly re-oxidation step. Electrical data and TEM analysis indicate that lateral oxygen diffusion was not an issue in EOT degradation. An asymmetric V/sub FB/ shift is observed for NMOS and PMOS transistors. The drive current for transistors with a high-k gate dielectric is improved by 10-15% with gate length scaling, but even for 70 nm gate length transistors it reaches only 60% of the SiON currents.
Keywords :
MOSFET; dielectric thin films; elemental semiconductors; hafnium compounds; silicon; 1.8 nm; 70 nm; EOT degradation; MOSFET gate stacks; NMOS transistors; PMOS transistors; Si-HfO/sub 2/; TEM analysis; gate length scaling; high-k gate dielectric; low thermal budget process; poly-Si gate electrode; polysilicon; self-aligned MOS process flow; transistor drive current; Electrodes; Gate leakage; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Leakage current; MOS devices; MOSFETs; Oxidation; Silicidation;
