Dual gate oxide charging damage in damascene copper technologies

Due to growing integrated circuit (IC) performance requirements, dual-gate oxide thickness and damascene-copper wiring are increasingly being employed by the IC industry. Charging damage behavior for 0.22-micron (3.5-nm oxide), 0.18-micron (2.7-nm/3.8-nm oxide), and 0.16-micron (3.5-nm/6.8-nm oxide) generation damascene-copper wiring technologies has been investigated. Charging damage manifests itself in four areas: elevated gate-oxide leakage currents, threshold voltage shifts, increased hot-carrier sensitivity, and early gate-oxide dielectric breakdown. The PFET devices generally displayed higher gate-oxide leakage currents, threshold-voltage shifts, and hot-carrier sensitivity than the NFET devices. For the dual-gate oxide thickness technologies, the thick oxide was more susceptible to charging damage than the thin oxide for a given oxide thickness. The thicker of the two oxides in the dual-gate oxide thickness technologies was invariably found to be more susceptible to charging damage, even when an oxide of that same thickness was damage-free in a single oxide-thickness technology. Charging damage had no measurable effect on the gate-oxide breakdown voltage distribution, although the NFET devices had more early breakdown voltage fails than the PFET devices