Parallel VLSI architecture for MAP turbo decoder

Turbo codes achieve performance near the Shannon limit. Standard sequential VLSI implementation of turbo decoding requires large memory and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for turbo decoding is described, comprising multiple SISO (soft-in soft-out) elements, operating jointly on one turbo coded block, and a new parallel interleaver. Latency is reduced up to twenty times and throughput for large blocks is increased up to five-fold relative to sequential decoders, using the same area of silicon, and achieving the same coding gain. The parallel architecture scales favourably - latency and throughput improve with growing block size and chip area.