Title :
Scaling impact on analog performance of sub-100nm MOSFETs for mixed mode applications
Author :
Garg, Mayank ; Suryagandh, Sushant S. ; Woo, Jason C S
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
The recent explosion in the demand for mobile telecommunication, computing and multimedia applications has resulted in much interest in system on chip (SOC) applications. In this work, an analysis of the analog characteristics of scaled MOSFETs is presented. An analog performance metric of intrinsic gain, f/sub T/, linearity, and g/sub m//I/sub ds/ ratio is considered. The effect of scaling on various trade-offs is presented It has been shown that while scaling gate length (L/sub g/) improves various trade-offs, scaling oxide thickness (T/sub ox/) and source/drain extension junction depth (X/sub j/) do not impact trade-offs significantly and they can be set by other constraints such as power supply and gate leakage currents.
Keywords :
MOSFET; semiconductor device models; 100 nm; MOSFET optimization; analog performance metric; analog performance scaling effects; gate leakage currents; gate length scaling; mixed mode applications; oxide thickness scaling; power supply; scaling trade-offs; source/drain extension junction depth; Computer applications; Explosions; MOSFETs; Measurement; Mobile computing; Multimedia computing; Multimedia systems; Performance gain; System-on-a-chip; Telecommunication computing;
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
DOI :
10.1109/ESSDERC.2003.1256891
