A 4.2 mW 5.7-GHz frequency synthesizer with dynamic-logic (TSPC) frequency divider

Author

Carmo, J.P. ; Mendes, P.M. ; Correia, J.H.

Author_Institution

Dept. Ind. Electron., Univ. of Minho, Guimaraes, Portugal

fYear

2009

fDate

25-27 May 2009

Firstpage

309

Lastpage

312

Abstract

This paper presents a phase-locked loop (PLL) used as a frequency synthesizer for a radio-frequency (RF) transceiver for use in the 5.7 ISM band, which were designed in the UMC RF 0.18 mum CMOS process. The PLL produces a set of different 16 digitally programmable frequencies in the [5424; 5830 MHz] frequency range. The low-power operation is achieved with the use of dynamic logic in the feedback path. Simulations shown a total power consumption of 4.2 mW. Target applications are wireless sensors and microsystems applications that need RF transceivers for operation in the 5.7 GHz band.

Keywords

CMOS integrated circuits; frequency dividers; frequency synthesizers; low-power electronics; phase locked loops; transceivers; UMC RF CMOS process; digitally programmable frequency; dynamic logic; dynamic-logic frequency divider; frequency 5.7 GHz; frequency 5424 MHz to 5830 MHz; frequency synthesizer; high-speed digital circuit; low-power operation; phase-locked loop; power 4.2 mW; power consumption; radio-frequency transceiver; size 0.18 mum; CMOS logic circuits; CMOS process; Energy consumption; Feedback; Frequency conversion; Frequency synthesizers; Phase locked loops; Radio frequency; Transceivers; Wireless sensor networks; CMOS; Frequency synthesizer; high-speed digital circuits; low-power design;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunications, 2009. ICT '09. International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4244-2936-3

Electronic_ISBN

978-1-4244-2937-0

Type

conf

DOI

10.1109/ICTEL.2009.5158664

Filename

5158664