From feature scale simulation to backend simulation for a 100 nm CMOS process

The current challenge for TCAD is the prediction of the performance of groups of devices, backends, and - generally speaking - large parts of the final IC, in contrast to the simulation of single devices and their fabrication. This enables one to predictively simulate the performance of the final device depending on different process technologies and parameters, which the simulation of single devices cannot achieve. In this paper, we focus on the simulation of backend, interconnect capacitance, and time delays. To that end, topography simulations of deposition, etching, and CMP processes in the various metal lines are used to build up the backend stack. The output of the feature scale simulations is used as input to a capacitance extraction tool, whose results are made available directly to the circuit designer. We discuss the utilized simulation tools and their integration. The topography simulations were performed by our tool called ELSA (enhanced level set applications) and the subsequent simulations by RAPHAEL. Finally simulation results for a 100 nm process are presented, where the influence of void formation between metal lines profoundly impacts the performance of the whole interconnect stack.