Closed-loop Built in Self Test for PLL production testing with minimal tester resources

Phase locked loops (PLLs) are extensively used in modern system on a chip (SoC) modules for generating timing, clock signal recovery and to provide a timing reference for communication interfaces. Due to their use in crucial and omnipresent applications, PLLs are the only mixed signal components on many otherwise digital blocks. The mixed signal nature makes testing of PLLs complicated as the output test requirements include non-digital parameters such as phase error, lock time, jitter along with the typical frequency locking test. Automatic test equipment (ATE) resources needed for these added parameters may require the use of a higher-end ATE for an otherwise digital block, driving up the production test costs. Built in self test (BiST) approaches for PLLs need to be carefully designed due to the load-sensitive nature of the internal analog nodes as well as sensitivity of the feedback path to any added delays by the BiST overhead. Our scheme proposes a mixed-signal closed loop complete test solution for a PLL by injecting a BiST signal at non-sensitive internal nodes and observing a low frequency(LF)/DC output in order to perform a pass/fail decision on the PLL. The goal of this scheme is to enable complete production quality at-speed testing of a PLL using minimal ATE resources.