Title :
Deep trench isolation for 600 V SOI power devices
Author :
Clavelier, L. ; Charlet, B. ; Giffard, B. ; Roy, M.
Author_Institution :
Silicon Technol. Dept, CEA/LETI, Grenoble, France
Abstract :
This paper describes the realization and characterisation of DTI (deep trench isolation) on thick (60 /spl mu/m) SOI (silicon on insulator) wafers for domestic and automotive applications. To this aim, DTI process optimisation and adaptation permits the identification of the key parameters in breakdown voltage capability. The role of different parts of the elaborated DTI was found to demonstrate the possibility of good results in breakdown voltage /sup p/ to 600 V.
Keywords :
isolation technology; optimisation; power semiconductor devices; semiconductor device breakdown; silicon-on-insulator; 60 micron; 600 V; SOI power devices; Si-SiO/sub 2/; breakdown voltage capability; deep trench isolation; process optimisation; thick silicon on insulator DTI; Anisotropic magnetoresistance; Dielectric substrates; Diffusion tensor imaging; Doping; Electrodes; Etching; Filling; Isolation technology; Plasma applications; Silicon on insulator technology;
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
DOI :
10.1109/ESSDERC.2003.1256922
