Design of high performance timing recovery loops for communication applications

Timing recovery in communication systems with linear modulations is usually performed with a non-data-aided feedback loop based on a fractional interpolator timing corrector and the Gardner´s timing error detector. The contribution of this paper is twofold. First, it is shown that pipelining can be used to reduce power consumption in a timing feedback loop. Second, some design rules are given to predict the behaviour of the loop if pipeline is used. A timing recovery loop has been implemented in an FPGA device and power consumption measures indicates that by including 16 extra registers in the loop the power consumption decreases a 63% and the synchronizer can process up to 66.5 MSPS