A Reconfigurable SOS-based Rayleigh Fading Channel Simulator

A channel simulator is essential in the development and accurate performance evaluation of wireless systems. This paper presents an improved hardware implementation of a Rayleigh fading channel simulator that uses only 13% of the Xilinx Virtex2P XC2VP100-6 field-programmable gate array (FPGA) and operates at up to 210 MHz, generating 210 million accurately distributed and correlated complex fading coefficients per second. Our fading channel simulator is 506 times faster than a software-based simulator written in C running on a 3.4-GHz Pentium 4 processor. The fading channel simulator layout in 90-nm CMOS technology occupies 967 mum² of silicon area when the operating rate target is 500 MHz