Title :
A flexible platform architecture for Gbps wireless communication
Author :
Declerck, Jeroen ; Avasare, Prabhat ; Glassee, Miguel ; Amin, Amir ; Umans, Erik ; Dewilde, Andy ; Raghavan, Praveen ; Palkovic, Martin
Author_Institution :
IMEC V.Z.W., Belgium
Abstract :
Reprogrammable radio platforms should not only offer flexibility and low power consumption but also conform to strict throughput and latency requirements mandated by the wireless standards. To achieve these challenging goals, we introduce a platform architecture that uses a decentralized control to minimize communication and control overhead while keeping timing predictable by using state-of-the-art components and a novel interconnect. We demonstrate three main achievements in running multiple wireless standards on our platform: 1.053Gbps 4×4 80MHz WLAN 802.11ac receiver data path meeting the SIFS timing with a latency of 12.5μs, dual concurrent 173Mbps 2×2 20MHz Cat-4 3GPP-LTE receiver and platform reconfiguration from WLAN 11n to 3GPP-LTE in 52μs. The main blocks from our versatile platform architecture are currently being prepared for tape-out.
Keywords :
3G mobile communication; Long Term Evolution; multiprocessing systems; multiprocessor interconnection networks; radio receivers; wireless LAN; 053Gbps 4×4 80MHz WLAN 802.11ac receiver data path; Gbps wireless communication; SIFS timing; dual concurrent 173Mbps 2×2 20MHz Cat- 4 3GPP-LTE receiver; flexible platform architecture; frequency 20 MHz; frequency 80 MHz; heterogeneous multiprocessor system-on-chip architecture; multiple wireless standard; novel interconnect; state-of-the-art component; Baseband; Computer architecture; Decoding; Standards; Synchronization; Wireless LAN; Wireless communication;
Conference_Titel :
System on Chip (SoC), 2012 International Symposium on
Conference_Location :
Tampere
Print_ISBN :
978-1-4673-2895-1
Electronic_ISBN :
978-1-4673-2894-4
DOI :
10.1109/ISSoC.2012.6376349