Effects of gate-currents on CMOS circuit behaviour

As the oxide thickness scales down to a few nanometers, gate currents become a major concern for circuit designers. In order to fully exploit the performance of such aggressively scaled devices, standard design flows, suitable for the design of actual digital systems, need to take into account such effects. In this paper, an approach to large-scale circuit simulation for ultrathin gate-oxide technologies is discussed, analysing the influence of tunnel currents on circuit performance. Device and circuit models for both permeable-and ideal-gate devices have been devised and characterized on the basis of actual measurements. As a test vehicle, a simple ring-oscillator has been simulated, accounting for gate oxides in the (1.5 nm>t/sub ox/>0.9 nm) thickness-range, and the impact of gate currents on major behavioural parameters has been analysed. Although circuit functionality is not compromised (within the considered technology range, at least), a non-negligible influence on circuit performance has been observed.