Efficient VLSI architectures of QPP interleavers for LTE turbo decoders

Quadratic-permutation-polynomial (QPP) interleavers are utilized in Turbo coding of the 4G-mobile-system LTE-Advanced due to the support of parallel, contention-free memory accesses. In principle, throughput rates of 1 Gbit/s can be supported with such interleavers in today´s CMOS technologies. A systematic examination of the QPP interleaver properties has led to several design improvements concerning silicon area, energy per operation and the support of highly parallelized Turbo decoders. Regarding the interleaver network, it is proven that hardware-efficient butterfly and Bene?s networks can be applied with negligible configuration overhead. With respect to the interleaver address generation, we propose and analyze a recursive address calculation method.