Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications

This paper presents a high-speed forward error correction (FEC) architecture based on the concatenated BCH code for 100-Gb/s optical communication systems. The concatenated BCH code consists of BCH (3860, 3824) and BCH(2040, 1930), which provides 7.98 dB net coding gain at 10^-12 corrected bit error rate without additive overhead as compared with the Reed-Solomon(255, 239) standardized in ITU-T G.975 and G.709. This architecture has been implemented with 90-nm CMOS standard cell technology in a supply voltage of 1.1 V. The implementation results show that the concatenated BCH super-FEC architecture can operates at a clock frequency of 400 MHz and has a throughput of 102.4-Gb/s for 90-nm CMOS technology.