DocumentCode :
2444109
Title :
A novel trace-pipelined binary arithmetic coder architecture for JPEG2000
Author :
Rhu, Minsoo ; Park, In-Cheol
Author_Institution :
Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
fYear :
2009
fDate :
7-9 Oct. 2009
Firstpage :
243
Lastpage :
248
Abstract :
Embedded block coding with optimized truncation (EBCOT) employed in the JPEG2000 standard accounts for the majority of the processing time, because the EBCOT is full of bit operations that cannot be implemented efficiently in software. The block coder consists of a bit-plane coder (BPC) followed by a binary arithmetic coder (BAC), where the most up-to-date BPC architectures are capable of producing symbols at a much higher rate than the conventional BACs can handle. This paper proposes a novel pipelined BAC architecture that can encode input symbols at a much higher rate than the conventional BAC architectures. The proposed architecture can significantly reduce the critical path delay and can achieve a throughput of 400 M symbols/sec. The critical path delay synthesized with 0.18-mum CMOS technology is 2.42 ns, which is almost half of the delay taken in conventional BAC architectures.
Keywords :
CMOS integrated circuits; arithmetic codes; block codes; image coding; CMOS technology; JPEG2000; bit-plane coder; embedded block coding; optimized truncation; trace-pipelined binary arithmetic coder architecture; Arithmetic; Block codes; CMOS technology; Computer architecture; Delay; Discrete wavelet transforms; Image coding; Motion pictures; Throughput; Transform coding; EBCOT; JPEG2000; VLSI architecture; arithmetic coding; trace scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 2009. SiPS 2009. IEEE Workshop on
Conference_Location :
Tampere
ISSN :
1520-6130
Print_ISBN :
978-1-4244-4335-2
Electronic_ISBN :
1520-6130
Type :
conf
DOI :
10.1109/SIPS.2009.5336259
Filename :
5336259
Link To Document :
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