Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems

FFT is one of the most widely used transformations in modern communication systems, especially those based on OFDM. At the same time, it is one of the largest and most power hungry parts of a modem and therefore any effort to reduce its area and energy footprint is highly desirable. In this paper, we propose the use of mixed linear and logarithmic arithmetic data representation in order to reduce the area and more importantly the energy consumption of a 64-point FFT implementation. By adopting BER as the metric to compare the equivalence between different implementations, we demonstrate that small words can be used throughout the FFT system and these allow the combination of a linear two´s complement fixed-point representation with LNS. For the same performance levels, this hybrid representation system requires 5% less area and consumes 23% less energy when compared with a pure linear representation implementation.