DocumentCode
2444323
Title
Desing and Optimization of a Programmable Instruction Decoder for DSP Architecture
Author
Jung, Yong-Kyu
Author_Institution
Texas A&M Univ.
fYear
2006
fDate
2-4 Oct. 2006
Firstpage
333
Lastpage
338
Abstract
A hardware/software co-reconfiguration technique is introduced to design a programmable instruction decoder for DSP systems that do not employ field-programmable gate-array. This technique allows software developers to swiftly and accurately retarget their DSP systems. In order to present the reconfiguration procedures and performance evaluations of the technique, a reconfigurable instruction decoder (RID) for Texas Instruments´ TMS320C55 DSPs was implemented and optimized
Keywords
decoding; digital signal processing chips; hardware-software codesign; instruction sets; TMS320C55 DSP; hardware-software coreconfiguration technique; programmable instruction decoder; Application software; Computer architecture; Costs; Decoding; Design optimization; Digital signal processing; Field programmable gate arrays; Hardware; Instruction sets; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on
Conference_Location
Banff, Alta.
ISSN
1520-6130
Print_ISBN
1-4244-0382-0
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2006.352604
Filename
4161874
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