Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio

Software defined radios (SDR) requires an application-specific programmable architecture with instruction set targeted toward wireless baseband processing. Enabling this in handhelds terminal asks for both energy-awareness and cost-effectiveness. Micro-architecture efficiency and software mapping productivity must be carefully balanced. Especially in exploiting data-level parallelism, one has to trade off explicit, user-defined subword parallelism and automated, compiler-driven instruction level parallelism. In this paper, we describe an extensive exploration of a scalable subword-parallelism-enabled very long instruction word architecture targeting 100 Mbps SDRs. Coware LISATek tools is used to model a VLIW processor with scalable number of SIMD units. A compilation flow is set up supporting advanced ILP scheduling and subword parallelism encapsulation through intrinsic functions. Based on a set of representative SDR benchmarks, application specific optimization is carried out introducing powerful instruction set extensions. Cost and benefits are evaluated in terms of benchmark execution time and energy. Therefore, RTL is generated from LISATek and synthesized using a 90 nm CMOS library. By varying the architecture and technology parameters the optimal energy-performance tradeoff is derived. The achieved performance is more than sufficient for SISO WLAN such as 802.11 a/g