DocumentCode
2444457
Title
Efficient simulation of QC LDPC decoding on GPU platform by CUDA
Author
Bin Jiang ; Jianrong Bao ; Xiaorong Xu
Author_Institution
Sch. of Telecommun. Eng., Hangzhou Dianzi Univ., Hangzhou, China
fYear
2012
fDate
25-27 Oct. 2012
Firstpage
1
Lastpage
5
Abstract
An efficient parallel simulation scheme of quasi-cyclic (QC) low-density parity-check (LDPC) decoding is proposed to improve the simulation efficiency greatly. It employs multi-threads with the multi-processors of a graphic processing unit (GPU) to perform the simulation of LDPC decoding in parallel. Other than full hardware based LDPC decoding, it obtains good features of low cost, easy programming complexity by using the compute unified device architecture (CUDA) techniques. The CUDA also provides parallel computing by the GPU with efficient multi-thread computation and very high memory bandwidth. Based on the proposed scheme, all bit nodes or check nodes can be updated in an LDPC decoding iteration simultaneously. Therefore, it provides an efficient and fast approach of QC LDPC decoding.
Keywords
cyclic codes; graphics processing units; iterative decoding; multi-threading; multiprocessing systems; parallel architectures; parity check codes; CUDA; GPU platform; QC LDPC decoding simulation; bit nodes; check nodes; compute unified device architecture techniques; graphic processing unit; memory bandwidth; multiprocessors; multithread computation; parallel computing; parallel simulation scheme; programming complexity; quasi-cyclic low-density parity-check decoding; simulation efficiency improvement; CUDA; GPU; LDPC codes; QC; parallel computation;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communications & Signal Processing (WCSP), 2012 International Conference on
Conference_Location
Huangshan
Print_ISBN
978-1-4673-5830-9
Electronic_ISBN
978-1-4673-5829-3
Type
conf
DOI
10.1109/WCSP.2012.6542885
Filename
6542885
Link To Document