A sub-0.5 V dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS technologies

Author

Elgebaly, Mohamed ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

fYear

2001

fDate

29-31 Oct. 2001

Firstpage

75

Lastpage

78

Abstract

A new dynamic threshold PMOS (DTPMOS) scheme is presented. In this scheme, the gate of a PMOS transistor is connected to its well in a conventional bulk CMOS technology. This technique results in improved switching speed compared to conventional CMOS in the sub-0.5 V regime. A 32-bit carry skip adder is designed for low voltage, low energy applications using the DTPMOS scheme. This adder consumes only 0.25 pJ of energy at a frequency of 5 MHz. The proposed design results in a 64% reduction in delay and 26% saving in energy compared to the conventional CMOS implementation.

Keywords

CMOS logic circuits; adders; carry logic; leakage currents; low-power electronics; 0.25 pJ; 0.5 V; 5 MHz; LV applications; carry skip adder; dynamic threshold PMOS scheme; leakage power reduction; low energy applications; low voltage applications; pass-transistor full adder circuit; switching speed; Adders; CMOS technology; Delay; Energy consumption; Frequency; Low voltage; MOSFETs; Silicon on insulator technology; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on

Print_ISBN

0-7803-7522-X

Type

conf

DOI

10.1109/ICM.2001.997491

Filename

997491