DocumentCode
2444553
Title
A VLSI 8Ã\x978 MIMO Near-ML Decoder Engine
Author
Knagge, Geoff ; Bickerstaff, Mark ; Ninness, Brett ; Weller, Steven R. ; Woodward, Graeme
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Newcastle Univ., NSW
fYear
2006
fDate
2-4 Oct. 2006
Firstpage
387
Lastpage
392
Abstract
Multiple-input multiple-output (MIMO) systems are of significant interest due to their ability to increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits. A particularly difficult part of these systems is the decoder, where the optimal maximum-likelihood (ML) solution is desirable, but cannot be directly implemented due to its exponential complexity. The paper presents the first published 8times8 MIMO detection engine with an integrated channel preprocessing unit, achieving near-ML BER results at 57.6 Mbps, using QPSK in an extended HSDPA application. Other novelties include the high speed sorting mechanism and power saving features
Keywords
MIMO communication; VLSI; maximum likelihood decoding; wireless channels; 57.6 Mbit/s; HSDPA application; MIMO near-ML decoder engine; QPSK; VLSI circuits; high speed sorting mechanism; integrated channel preprocessing unit; multiple-input multiple-output system; optimal maximum-likelihood solution; power saving features; very large scale integration; wireless communication system; Bit error rate; Circuits; Engines; MIMO; Maximum likelihood decoding; Maximum likelihood detection; Multiaccess communication; Quadrature phase shift keying; Very large scale integration; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on
Conference_Location
Banff, Alta.
ISSN
1520-6130
Print_ISBN
1-4244-0382-0
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2006.352614
Filename
4161884
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