Comparison of bulk and SOI CMOS technologies in a DSP processor circuit implementation

Silicon-on-insulator (SOI) CMOS technologies are very attractive options for implementing high-speed digital integrated circuits for low-power applications. This paper presents the layout migration of a DSP processor chip from a 0.6 μm bulk CMOS to a 0.5 μm SOI CMOS technology. The layout migration and verification are described and the two CMOS designs are compared using two main criteria: circuit speed and average power consumption. For nominal supply voltages, the simulations suggest that the SOI circuit can operate at a speed of 98 MHz which is 51 % higher than that of the original (65 MHz). The average power consumption is 35 % lower in the SOI circuit by using 3.3 V and 35 MHz for both SOI and bulk CMOS designs.