An area-efficient hexagonal interconnection network for multi-core processors

With the rapid increase in the number of processor cores on a chip, packet-switching networks on chip (NoCs) have emerged as a promising paradigm for designing scalable communication infrastructures for future multi-core processors. The quest for high-performance networks, however, has led to very area-consuming and complex routers with marginal return in performance. On the other hand, studies show that real parallel applications generate traffic at a much lower rate than the offered rate at the cost of expensive and power-hungry buffers. This paper presents a low-cost hexagonal network design with only one buffer in each router. Efficient routing algorithms are proposed. Extensive simulation results with a 19-node network show that our network, in addition to its lower cost, provides low network latency under low to medium network load, which matches the communication requirement imposed by applications for multicore processors.