Low-power vectorial VLIW architecture for maximum parallelism exploitation of dynamic programming algorithms

Dynamic Programming algorithms are widely used in many areas, to divide a complex problem into several simpler sub-problems, with many dependencies. Typical approaches explore data level parallelism by relying on spacialized vector instructions. However, the fully-parallelizable scheme is often not compliant with the memory organization of general purpose processors, leading to a less optimal parallelism, with worse performance. The proposed architecture exploits both data and instruction level parallelism, by statically scheduling a bundle of instructions to several different vector execution units. This achieves better performance than vector-only architectures, and has lower hardware requirements and thus lower power consumption. Performance and energy efficiency metrics were used to benchmark the proposed architecture against a dual issue, out-of-order ARM Cortex-A9 and a dedicated ASIP architecture. In a fair comparison where all processors compute 16 dynamic programming cells in parallel, results show that the proposed architecture can achieve a 3.24x and 2.35x better performance-energy efficiency than the ARM Cortex-A9 and the dedicated ASIP, respectively, and a performance improvement of 2.54x and 5.01× regarding the ARM and the dedicated ASIP, respectively.