Methodology and technique to improve throughput of FPGA-based Cal dataflow programs: Case study of the RVC MPEG-4 SP Intra decoder

The specification of complex signal processing systems in hardware by means of HDL is no longer the appropriate way since they are known to be time consuming to design, and less flexible to extend features. Recently, Cal dataflow language was specified to increase productivity and scalability, with ability to synthesize to HDL for hardware implementation. In this paper, a new methodology to improve throughput of dataflow-based hardware designs is given by analyzing Cal programs using the profiling tool. As a case study, we analyzed the RVC MPEG-4 SP Intra decoder and found that the texture decoding part has the highest improvement factor. We have also introduced the luminance texture splitting technique as the improvement method by increasing the level of parallelism in the decoder. Experimental results of implementation on Virtex-5 FPGA confirmed our analysis with throughput increase of up to 50.5% with only 4.3% additional slice.