Efficient multicore scheduling of dataflow process networks

Author

Yviquel, Hervé ; Casseau, Emmanuel ; Wipliez, Matthieu ; Raulet, Mickaël

Author_Institution

IRISA, Univ. of Rennes 1, Lannion, France

fYear

2011

fDate

4-7 Oct. 2011

Firstpage

198

Lastpage

203

Abstract

Although multi-core processors are now available everywhere, few applications are able to truly exploit their multiprocessing capabilities. Dataflow programming attempts to solve this problem by expressing explicit parallelism within an application. In this paper, we describe two scheduling strategies for executing a dataflow program on a single-core processor. We also describe an extension of these strategies on multi-core architectures using distributed schedulers and lock-free communications. We show the efficiency of these scheduling strategies on MPEG-4 Simple Profile and MPEG-4 Advanced Video Coding decoders.

Keywords

data flow computing; multiprocessing systems; parallel architectures; processor scheduling; MPEG-4; advanced video coding; dataflow process networks; dataflow program; multicore architectures; multicore processor; processor scheduling; single core processor; Decoding; Dynamic scheduling; Instruction sets; Multicore processing; Processor scheduling; Transform coding; Dataflow computing; Distributed algorithm; Lock-free multithreading; Multicore processing; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems (SiPS), 2011 IEEE Workshop on

Conference_Location

Beirut

ISSN

2162-3562

Print_ISBN

978-1-4577-1920-2

Type

conf

DOI

10.1109/SiPS.2011.6088974

Filename

6088974