The SOC design and implementation of digital protective relay based on IP cores

In this paper, a method of system on chip (SOC) design based on IP cores for digital protective relay is presented. Compared with a microprocessor, SOC provides many benefits: reduced product cost and reduced complexity due to the integration of the logic functions in a fewer devices, improved reliability and increased system availability, increased data processing speed, and reduced time-to-market due to the more flexible design. The major design tasks are defining and implementing each IP core. Some typical IP cores, such as data acquisition control block, data processing block, algorithm for protection block, data distribution and procedure management block are introduced in this paper. By integrating these IP cores, we have implemented a chip for power transmission line protection. The result of hardware simulation on FPGA and the experiments on apparatus, which based on SOC shows that our design is perfect. The chips for other power equipment protection can also be implemented by just changing some algorithm blocks and reconfiguring data distribution and procedure management block.