Title :
A Linearized Model for the Design of Fractional-
Digital PLLs Based on Dual-Mode Ring Oscillator FDCs
Author :
Weltin-Wu, Colin ; Familier, Eythan ; Galton, Ian
Author_Institution :
Electr. & Comput. Eng., Univ. of California, San Diego, Jolla, CA, USA
Abstract :
A digital fractional- N phase-locked loop (PLL) frequency synthesizer based on a second-order ΔΣ frequency-to-digital converter (FDC) without conventional analog components was recently proposed and demonstrated experimentally to have performance in line with state-of-the-art analog PLLs. However, unlike analog PLLs or prior PLLs based on second-order ΔΣ FDCs, it is highly digital and does not require an analog charge pump or ADC, so it is well-suited to implementation in highly-scaled CMOS technology. This paper derives a linearized model of the new architecture and key equations which are necessary for the design of PLLs based on the architecture.
Keywords :
delta-sigma modulation; digital phase locked loops; frequency synthesizers; integrated circuit design; linearisation techniques; analog PLL; analog components; digital fractional-N phase-locked loop frequency synthesizer; dual-mode ring oscillator FDC; fractional-N digital PLL; highly-scaled CMOS technology; linearized model; second-order ΔΣ FDC; second-order ΔΣ frequency-to-digital converter; Charge pumps; Modulation; Noise; Phase frequency detector; Phase locked loops; Quantization (signal); Radiation detectors; Delta-sigma; FDC; digital PLL; frequency synthesizer;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2015.2440737