System integration of the VLSI-PLM chip

The design and building of an interface system for the VLSI-PLM (Prolog Machine) chip, a high-performance CMOS processor for executing Prolog, are described. The interface system plugs into a Sun 3/160 host. Two versions of this system have been designed: a wire-wrapped board and a printed circuit board. First, the design and simulations were done using Mentor Graphics computer aided design tools on Apollo workstations. By using these tools, it was possible to draw the gate-level design schematics on the computer and simulate the functionality and timing of the design. After the gate-level design passed all simulation tests, a wire-wrapped board was constructed. Testing the wire-wrapped board verified the computer simulations of the gate-level design. Second, the gate-level design was transformed into a PCB design using the MG Board Station tool. This tool allows one to package the design´s TTL parts into PCB parts, place and route the PCB, create manufacturing data, and simulate the design at the board-level. In building complex systems, some critical parts should be bread-boarded to validate simulations before fabricating a PCB