• DocumentCode
    2446035
  • Title

    A GPU-inspired soft processor for high-throughput acceleration

  • Author

    Kingyens, Jeffrey ; Steffan, J. Gregory

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
  • fYear
    2010
  • fDate
    19-23 April 2010
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely highly-parallel and pipelinable computation. In particular, our soft processor architecture exploits multithreading and vector operations to supply a floating-point pipeline of 64 stages via hardware support for up to 256 concurrent thread contexts. The key new contributions of our architecture are mechanisms for managing threads and register files that maximize data-level and instruction-level parallelism while overcoming the challenges of port limitations of FPGA block memories, as well as memory and pipeline latency. Through simulation of a system that (i) supports AMD´s CTM r5xx GPU ISA , and (ii) is realizable on an XtremeData XD1000 FPGA-based accelerator system, we demonstrate that our soft processor can achieve 100% utilization of the deeply-pipelined floating-point datapath.
  • Keywords
    computer graphic equipment; coprocessors; field programmable gate arrays; multi-threading; parallel processing; pipeline processing; AMD CTM r5xx GPU ISA; GPU; XtremeData XD1000 FPGA-based accelerator system; floating-point pipeline; graphics processing units; high-throughput acceleration; highly-parallel computation; instruction-level parallelism; multithreading process; pipelinable computation; soft processor programming; Acceleration; Buildings; Computer architecture; Field programmable gate arrays; Graphics; Hardware; Memory management; Multithreading; Pipelines; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on
  • Conference_Location
    Atlanta, GA
  • Print_ISBN
    978-1-4244-6533-0
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2010.5470679
  • Filename
    5470679