A compact, low-power low-jitter digital PLL

Author

Fahim, Am M.

Author_Institution

Qualcomm Inc., San Diego, CA, USA

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

101

Lastpage

104

Abstract

This paper describes a compact, low-power and low-jitter digital PLL (DPLL). Digitizing the loop filter presents numerous challenges and advantages. In the proposed scheme, a wide-band DPLL is described that achieves low-jitter and low-power consumption. Low-jitter is achieved by using an all-digital adaptive bandwidth control scheme that can track the noise injected into the DPLL and optimize the loop bandwidth accordingly. A prototype DPLL employing has been implemented in a 0.25/spl mu/m CMOS technology. Measurement results show that jitter 130ps jitter is achieved at 144MHz. The area and power consumption outperform the traditional charge-pump based PLL by a factor of 3.5/spl times/ and 45% respectively.

Keywords

CMOS digital integrated circuits; circuit optimisation; digital phase locked loops; low-power electronics; power consumption; 0.25 microns; 144 MHz; CMOS technology; all-digital adaptive bandwidth control scheme; charge-pump PLL; compact digital PLL; loop bandwidth optimization; loop filter digitizing; low-jitter digital PLL; low-power consumption; low-power digital PLL; wide-band DPLL; Adaptive control; Bandwidth; CMOS technology; Filters; Jitter; Phase locked loops; Programmable control; Prototypes; Tracking loops; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257082

Filename

1257082