DocumentCode
2446442
Title
Design of high gain fully-integrated distributed amplifiers in 0.35 /spl mu/m CMOS
Author
Amaya, Rony ; Plett, Calvin
Author_Institution
Carleton Univ., Ottawa, Ont., Canada
fYear
2003
fDate
16-18 Sept. 2003
Firstpage
145
Lastpage
148
Abstract
A 3.3V single-supply fully-integrated distributed amplifier was implemented in a standard 0.35 /spl mu/m CMOS process up to 20 dB of gain and a bandwidth of 5.5 GHz. This is the highest reported gain for a CMOS distributed amplifier. Octagonal inductors with no ground shield were implemented in top available metal. Design guidelines for optimizing amplifier gain are presented. Chip dimensions are 0.95 /spl times/ 1.8 mm/sup 2/ and power dissipation is 86.7 mW, drawn from a 3.3V supply.
Keywords
CMOS integrated circuits; circuit optimisation; distributed amplifiers; inductors; 0.35 microns; 3.3 V; 5.5 GHz; 86.7 mW; CMOS distributed amplifier; amplifier gain optimization; design guidelines; fully-integrated distributed amplifiers; ground shield; high gain distributed amplifier; octagonal inductors; single-supply distributed amplifier; top available metal; Bandwidth; CMOS process; Capacitance; Costs; Distributed amplifiers; FETs; Frequency; Inductors; Q factor; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location
Estoril, Portugal
Print_ISBN
0-7803-7995-0
Type
conf
DOI
10.1109/ESSCIRC.2003.1257093
Filename
1257093
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