17GHz and 24GHz LNA designs based on extended-S-parameter with microstrip-on-die in 0.18/spl mu/m logic CMOS technology

In a marked departure from traditional microwave design approaches, we present S-parameter based designs for 17GHz and 24GHz LNAs where the size of active devices is a design\´s degree of freedom and passives on the CMOS die are significant noise contributors, due to their low Q. Because of the low Q passives, design method includes (a) backing off from transistor\´s NFmin, and (b) proper choice of transistor size to minimize length (i.e. losses) of the microstrips-on-die. High performance logic 0.18/spl mu/m CMOS technology is used, digital layout design rules are enforced and sharp turns are used in all microstrip-on-die passives. The distributed on-die passives have been used to realize robust, low inductance values (as low as 25pH) in a "correct-by-construction" approach. Both LNAs reach NF of 5-6dB, only 2-3dB above the active devices minimum noise figure, the best results known to the authors at these frequency of operation using 0.18/spl mu/m CMOS technology. IP3 is as high as -3dBm. Both LNAs operate at frequencies around 1/3 of the CMOS transistor\´s f/sub t/ (60GHz).