The Hardware Design and Implementation of a Signal Reconstruction Algorithm Based on Compressed Sensing

A fast and reliable signal reconstruction algorithm is the core part of the compressed sensing (CS) theory. As a reconstruction algorithm, interior point method has a high precision but it is time-consuming and needs large computation, so it is difficult to meet the actual needs. In view of the above problems, in this paper we propose a design for interior point method that is based on the Field Programmable Gate Array (FPGA )hardware platform, which is about the solution of linear equations that have the largest amount of computation. The array structure of the conjugate gradients (CG) coprocessor completes the main operations, and the parallel and pipeline coprocessor effectively take advantage of the inherent parallelism of the algorithm and the parallel structure of FPGA. Thus, it has greatly improved the processing speed.