Energy minimization method for optimal energy-delay extraction

Author

Dao, Hoang Q. ; Zeydel, Bart R. ; Oklobdzija, Vojin G.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

177

Lastpage

180

Abstract

In evaluating a design, it is critical to extract the best energy-delay curve, often performed with optimization tools. Such curve can be quickly obtained from our proposed numerical method where the energy at each delay target is minimized by redistribution of gate sizes to balance delay and energy consumption among different stages of the design. Compared to delay-optimized solution, the resulting energy saving is significant, 30%-50%, depending on delay target and design. The results are confirmed with simulation, using Fujitsu´s 0.11/spl mu/m, 1.2V CMOS technology.

Keywords

CMOS integrated circuits; circuit optimisation; delay circuits; energy conservation; logic design; minimisation; 0.11 microns; 1.2 V; CMOS technology; balance delay; delay design; delay target; delay-optimized solution; energy consumption; energy minimization method; energy-delay curve; gate sizes redistribution; numerical method; optimal energy-delay extraction; optimization tools; Adders; CMOS technology; Circuit testing; Delay estimation; Design optimization; Energy consumption; Minimization methods; Optimization methods; Performance evaluation; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257101

Filename

1257101