A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies

In high performance designs, dynamic circuits, such as domino logic, are used because of their high speed. However, due to its low noise margin, domino circuits do not scale effectively. Skewed logic circuit can be used to achieve design having performance comparable to that of domino but with better scalability. We proposed selectively clocked skewed logic (SCSL) as an alternative to domino logic for high-performance, noise-immune, low-power circuits. Moreover, a time borrowing technique that is usually used in domino designs can also be applied to further improve the performance of SCSL circuits. This paper proposes time borrowing selectively clocked skewed logic (TB-SCSL) style for high-performance applications. Results from the simulation on 16-bit carry lookahead adders (CLA) in 0.25/spl mu/m technology show that TB-SCSL can achieve approximately 15% higher performance compared to the normal SCSL.