Title :
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies
Author :
Sirisantana, Naran ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
In high performance designs, dynamic circuits, such as domino logic, are used because of their high speed. However, due to its low noise margin, domino circuits do not scale effectively. Skewed logic circuit can be used to achieve design having performance comparable to that of domino but with better scalability. We proposed selectively clocked skewed logic (SCSL) as an alternative to domino logic for high-performance, noise-immune, low-power circuits. Moreover, a time borrowing technique that is usually used in domino designs can also be applied to further improve the performance of SCSL circuits. This paper proposes time borrowing selectively clocked skewed logic (TB-SCSL) style for high-performance applications. Results from the simulation on 16-bit carry lookahead adders (CLA) in 0.25/spl mu/m technology show that TB-SCSL can achieve approximately 15% higher performance compared to the normal SCSL.
Keywords :
adders; circuit noise; logic circuits; logic design; logic simulation; low-power electronics; 0.25 microns; 16 bit; SCSL circuits; carry lookahead adders; domino designs; domino logic; dynamic circuits; high performance designs; high-performance applications; high-performance circuit; high-performance circuits; low noise margin; low-power circuits; noise-immune circuit; scaled technologies; skewed logic circuit; time borrowing selectively clocked skewed logic; time borrowing technique; CMOS logic circuits; Circuit noise; Circuit topology; Clocks; Logic circuits; Logic design; Logic gates; MOSFETs; Propagation delay; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257102
