High performance pipelining method for static circuits using heterogeneous pipelining elements

A high performance pipelining method for static circuits is investigated using heterogeneous pipelining elements. This method selectively uses pulse flip-flops and master-slave flip-flops in the pipeline to optimize speed, power and robustness. Critical paths in the pipeline logic are terminated by pulse flip-flops to make them skew tolerant and to allow them to steal time from the next pipeline stage. Non-critical fast paths are terminated by master-slave flip-flops to keep their advantages of smaller area and power, and better robustness. Thus this method exploits best of MS flip-flops and pulse flip-flops to improve overall design cost and performance. We implemented a DSP using this methodology for analysis, which shows a reduction in the pipelining overhead by a factor of 3 at the cost of 7% increase in the area. We show that this method is fully compatible with the flip-flop based CAD flow making it useful for both processors as well as high performance ASICs.